Zynq UltraScale+ RFSoC ZCU208 Evaluation Kit

Digital Front End (DFE) Demo Lounge

Michal Gaska - High speed digital electronics design

XCKU014 1.5 Gsps, 1 board with FPGA and 1 with ADCs and DACs

RFSoc reduce latency by elinating JESD20-4B

dBc/Hz is the most meaningnful metric, higher sampling freq helps some. -150 dBc/Hz, large 1/f noise

100 nsec latency RF to RF Marble

JSD FMC120, 500 nsec latency, JESD buffers to align links so serial links adding latency

UC208 measurement latency was 200-300 nsec latency

higher pdiss, unknown noise density currently working to characterize

crosstalk is simular to Marble

chance of spurs goes up for using ADCs instead of mixers, jitters in the femotsec rnage

~6k cost, ~2 revisions, 4-6 months for first revision

Get the marble board from Larry's desk

just an FPGA board plus: